Signature rollback with extreme compaction —
A technique for testing robust VLSI circuits with reduced hardware overhead

Abstract. With the decreasing feature size of today's nanoelectronic circuits, the susceptibility to transient failures increases. New robust and self-adaptive designs are developed, which can handle transient error to some extent, but at the same time make testing for permanent faults more difficult. This paper reviews the “signature rollback” scheme as a strategy to minimize both test time and yield loss. The main idea is to partition the test into shorter sessions and immediately repeat sessions with a faulty result to distinguish between permanent defects and transient failures. While a high number of test sessions leads to a high test quality, the hardware overhead also increases. For this, an extreme compaction method is added which reduces the amount of data to be stored on chip without any degradation of the product quality.